By: Ethan Gallagher

(SeaPRwire) –   Automotive IC design teams have been stuck with a terrible tradeoff for years. They either modify qualified process PDKs to add embedded flash, or eat extra BOM costs for discrete memory parts. I’ve seen three separate power management IC projects hit 12+ week delays in the last six months over exactly this issue.

Tokyo-based eFlash IP developer Floadia announced its G1 automotive IP on June 18, 2026, built for TSMC’s 180BCD Gen3 platform. The IP combines 256KB program flash and 1KB data flash with 100K program/erase cycles, using proven SONOS technology. It requires zero modifications to TSMC’s existing standard PDK, and has passed full AEC-Q100 Grade 1 qualification. It also features a sub-20ms maximum erase time, integrated charge pump, and 8 parity-bit ECC for data integrity.

What Floadia didn’t shout in its press release is how big of a shortcut this creates for design teams. TSMC’s 180BCD Gen3 is already the dominant node for low to mid-tier automotive analog and power ICs. Most teams already have fully qualified workflows built around the existing PDK. Adding embedded flash without re-qualifying the entire process cuts 3 to 6 months off average tapeout timelines, and eliminates the need for external high-voltage circuitry or discrete EEPROM chips. Floadia’s core engineering team cut their teeth on embedded memory at Hitachi and Renesas, so the tech has decades of real-world testing behind it.

This release will lock TSMC’s 180BCD Gen3 as the default platform for mass-market automotive peripheral ICs for the next five years, and push smaller, unqualified eFlash IP vendors out of this high-volume segment entirely.

Author bio: Ethan Gallagher, a Silicon Valley hardware architect and infrastructure strategist focused on automotive semiconductor supply chain optimization.